The GPU Tsunami: TSMC, Intel, and Samsung Foundry
How AI silicon is turning foundry from wafer capacity into platform capacity
We continue our series on the GPU Tsunami within the framing that the GPU (thanks to AI) was the spark that set the entire industry on fire. Our first report in this series looked at how power semiconductors and analog control are benefiting from this dynamic. Higher rack density turns electricity delivery into a larger semiconductor problem. This report follows the same wave upstream into foundry, where the issue is different but the driver is the same: AI demand is exposing a layer of the supply chain that was not built to scale this fast.
There is more leading-edge wafer demand than TSMC can serve alone. Our ballpark estimate is that demand is running at 110–120% of available capacity, with AI accelerators, custom ASICs, mobile, and CPUs all competing for the same advanced-node base. Samsung and Intel do not need to displace TSMC to matter. They need to become usable where TSMC is constrained, expensive, or strategically concentrated.
The other dynamic to appreciate is a change in what the customer buys. Wafer supply, process leadership, and cost per transistor are still important, but they describe a shrinking share of the purchase decision process. Foundry is moving from chip-level manufacturing to system-level capacity. Customers are buying a more complete path to deployable AI silicon, where wafer supply, advanced packaging, memory integration, qualification, delivery timing, and acceptable geography have to line up together.
Chiplets (disaggregated design) are what make this chips to systems platform shift evident. They are still rare by count, likely under 1% of total semiconductor units and perhaps 10–20% of HPC/AI processor shipments, but they already carry 20–35% of semiconductor revenue and an even higher share of leading-edge compute value. In the angstrom era we expect more high-performance silicon to be built as systems of dies, memory, and packaging rather than as single monolithic chips. A dynamic that benefits Intel and Samsung.
TSMC remains the default. It leads in market share, profit share, yield, ecosystem depth, and packaging scale. AI has made that position more valuable. When compute revenue is gated by silicon supply, customers have less room to resist price increases. That is why advanced-node pricing power has become more visible.
Packaging is the second moat. The company that controls the packaging slot helps decide which customer ships. TSMC sells the wafer and the slot as one platform, and our model suggests packaging is the faster-growing layer of that platform. The market still tends to score foundry on wafer share. We think the scoreboard now includes packaging capacity, HBM integration, chiplet assembly, supply assurance, and geography.
That is where Samsung and Intel become more interesting. They are usually framed as second sources, but that misses the jobs customers may hire them to do. The question is not only who has the best transistor. It is what problem the customer needs solved.
Samsung is the integration option. Logic, HBM, packaging, and Taylor give it a turnkey AI pitch. For custom ASIC teams, automotive programs, and customers constrained by HBM access, one accountable supplier has value. The gaps are still real: advanced-node yield needs to improve, and external packaging capacity remains far below TSMC’s. Tesla and Groq help validate the direction, but they are not yet volume proof.
Intel is the packaging and geography option. External foundry revenue is still small, so the near-term wedge is not broad wafer share. It is EMIB-T, advanced packaging, and US supply assurance. A hyperscaler can send packaging work to Intel without committing a flagship die to an unproven external node. That is why judging Intel only on 18A wafer share misses the first part of the ramp.
The swing factor is TSMC. If CoWoS and SoIC scale fast enough to absorb the bottleneck, scarcity fades and challenger urgency falls. That same data point is TSMC upside and Samsung/Intel downside. The remaining opportunity for Samsung and Intel sits in the lanes where they can compete on technical merit and become first choice for a specific job, rather than simply second source to the default platform.
If interested in the full foundry model, please inquire.
What’s in the full report:
The TSMC platform revenue bridge, 2025–2030: leading-edge wafer revenue and advanced packaging modeled separately, with the attach ratio that most coverage misses.
The 2028 scenario model: bear, base, and bull platform revenue for TSMC, Samsung, and Intel, with the yield and packaging variables that swing the challenger numbers threefold.
The advanced packaging capacity roadmap: CoWoS/SoIC, EMIB/EMIB-T, I-Cube/SAINT, and OSAT spillover, year by year through 2030.
How to assess the three foundry exposures: the evidence each name reprices on, and on which quarterly clock.
A signal and read-through table for the next four to six quarters: which data updates move which thesis, and in which direction.
A confidence-weighted map of twelve customer engagements: what is confirmed, what is only reported, and what should not be modeled at all.
What would change our view: the specific falsifiers for each name, including the one TSMC data point that would damage the thesis most.