GPU Tsunami Beneficiaries: Power Semis and Analog
How AI Racks Pull Power Semiconductors and Analog Control Into a New Demand Cycle
We call what has happened in the semiconductor industry the GPU Tsunami. The GPU + AI was the initial shockwave and the chart below is the visual of the aftershock. Historical semiconductor cycles, which were usually tied to PCs, handsets, memory, or industrial and automotive demand at kept the industry at steady but slow growth. The GPU+AI moment shocked the industry and the entire semiconductor industry is growing at an unprecedented rate. The GPU is still the fuel, the center of gravity, but the demand it creates travels through hundreds of layers of the semiconductor supply chain: memory, substrates, packaging, networking, timing, power delivery, analog control, passives, thermal systems, test, WFE, and the mature-node capacity that supports much of the physical infrastructure around the accelerator.
That is where the cycle starts to get more interesting for all industry stakeholders. The obvious AI beneficiaries have already been heavily debated and largely mapped by us and others. The more interesting question to us is which parts of the semiconductor supply chain are being pulled into a new growth curve even though they do not screen like AI businesses at first glance. Power semiconductors and analog control sit near the top of that list.
A GPU creates the load, but it cannot use electricity in the form it arrives from the grid. Power has to be converted, stepped down, regulated close to the die, sensed, protected, and monitored continuously. As AI racks move from roughly 100kW-class systems toward several hundred kilowatts and eventually toward megawatt-class designs, that power tree becomes more complex and more semiconductor-rich. Content per rack rises because the system needs more point-of-load regulation, more intermediate bus conversion, more protection, more telemetry, and more analog control to make the accelerator usable at density.
That point becomes easier to see when you look directly at the power delivery hardware around a next-generation GPU tray. The photo below shows dense capacitor banks sitting immediately adjacent to a Vera Rubin GPU tray. Those cans are not the regulators themselves, and the voltage markings should not be added up as a direct power calculation. A 16V or 63V marking is a component rating, not the rail’s wattage. But the density is still insightful for our thesis. Many dozens of 100µF-class polymer capacitors sit beside each GPU power zone, likely supporting a mix of intermediate and local rails, absorbing fast current swings, reducing ripple, and giving the voltage regulators enough local energy storage to keep the GPU stable during abrupt workload transitions.
This is a Vera Rubin + Vera CPU compute trey in an HP Cray design. OEM/ODM builds will vary.
That is the physical version of the thesis. AI power content is not just moving into the PSU, the sidecar, or the facility layer. It is moving onto the tray, potentially the substrate, and closer to the accelerator. Each generation requires more regulated, sensed, buffered, protected, and telemetry-managed power within inches of the die. For analog and power semiconductor suppliers, rising rack power translates into a larger and more complex control problem. Every additional watt moving through the rack has to pass through layers of conversion, regulation, sensing, protection, and telemetry before it can be turned into usable compute.
Analog and power are different from the parts of the semiconductor industry investors tend to associate with fast AI scaling. Logic can often ride leading-edge process roadmaps, large platform concentration, and aggressive foundry capacity plans. Analog and power scale through a more physical supply chain: mature-node capacity, high-voltage process know-how, 200mm and 300mm power-device fabs, SiC and GaN material availability, thermal packaging, passives, magnetics, test, and long customer qualification cycles. The dirty secret is that analog often scales less cleanly than logic—it is also much harder from a design and engineering standpoint. It stays closer to the physics, where noise, heat, voltage behavior, layout, and process variation can determine whether a part works at spec. That makes the supply response slower when demand suddenly accelerates. Huge opportunity for agentic EDA here:
That makes power and analog a fascinating layer in the giga cycle. ASPs can rise when supply tightens, but the better point is that these components become part of the deployment math—and—a highly specific engineering challenge. A rack can have the right accelerator, memory, and networking, and still be limited by whether the power delivery architecture can support the density. That is the part of the GPU tsunami we focus on in this report: how AI rack density pulls power semiconductors and analog control into a demand cycle that is still under-discussed relative to how much it affects the rest of the build.
While this report is focused on power and analog attach to compute racks, we have a full report on 800 VDC beneficiary ecosystem.
What’s in the full report:
For paying subscribers, the full report goes deeper into the model, the rack architecture, and the supplier map. Inside we cover:
Our direct AI datacenter power semiconductor and analog control TAM model from 2025 to 2030.
Why stage 2 point-of-load power and intermediate bus conversion capture the largest share of direct semiconductor value.
How rack density changes the BOM as systems move from 100kW-class racks toward 600kW and 1MW-class architectures.
Why 48V and 54V distribution start to run out of room as current, copper, heat, and rack volume become limiting factors.
How 800V DC should be understood as a capacity architecture rather than only an efficiency upgrade.
The “power tree” from grid to core, including AC/DC, sidecars, IBC, point-of-load, protection, telemetry, and buffering.
The analog control layer: hot swap, eFuse, current sensing, isolation, digital power control, PMICs, and telemetry.
The role of BBU, CBU, and power smoothing as AI workloads become more dynamic.
A socket-level beneficiary map separating silicon / analog control, power modules / sidecar components, and datacenter power systems.
The risks and watch items that could change the slope of the thesis, including architecture timing, multi-sourcing, qualification cycles, and whether power vendors begin disclosing AI-specific revenue separately.